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Computation delay in digital systems translates to additional phase loss. This phase loss at any frequency f is given by 360*f/fs, where fs is the digital loop sampling frequency. So if we can maintain high fs compared to the bandwidth fc then the phase margin reduction caused by the delay at the crossover frequency (fc) is minimized. This also means that for high BW digital system the delay must be minimized as Ron entioned.Digital gives some advantage while closing some loops. For ex, UPS output voltage loop the integrator in the compensator can be changed to provide high gain at the UPS output frequency and not necessarily at DC. For high Q buck, digital allows for better loop response by use of complex zero compensation. This can also be used in PFC current loop or Solar inverter current loop with LCL type output filter.